The present invention relates in general to semiconductor power devices. More particularly, the invention provides structures and methods for a high voltage laterally diffused metal oxide semiconductor (LDMOS) device.
High voltage LDMOS transistors are finding increasingly broad applications in modern electronics, such as portable consumer electronics, power management circuits, automotive electronics, disk drives, display devices, RF communication circuits, and wireless base station circuits, etc. In these applications, the performance of an LDMOS transistor is usually measured by its on-resistance, switching speed, and breakdown voltage.
FIG. 1 is a cross-sectional view of a conventional high voltage LDMOS transistor 100. An n−-type well region 12 is formed on an n-type substrate 10. A p−-type body region 13 is formed in n−-type well region 12. An n+-type source region 15 and an n-type lightly doped source region 16 are formed in p−-type body region 13. An n-type lightly doped drain region 18 is formed in n−-type well region 12.
A gate insulating layer 20 extends over n−-type well region 12 and a surface portion of p-type body region 13. A gate conductive layer 21 extends over gate insulating layer 20. A source electrode 23 is in contact with n+-type source region 15 and p-type body region 13. An n+-type sinker region 20 connects the n-type lightly doped drain region 18 with the n+-type substrate 10, which is used as a drain electrode.
Upon applying a reverse bias across the drain-source electrodes, a depletion region extends out from the junction between p-type body region 13 and n-type well region 12, as shown by the arrow 32. High electric fields tend to build up in the depletion region, and breakdown occurs when the electric fields exceed certain limitations. When device 100 is turned on, the current flows from the drain region 10 through the sinker region and channel region to the source electrode 23. This current path often introduces a high on-resistance Rdson. Additionally, the charges in the well region and the body region can limit the switching speed of the device, when a gate voltage is applied to turn on and off the device.
Even though conventional LDMOS devices, such as device 100 in FIG. 1, are satisfactory in certain applications, they suffer from many limitations. These limitations include low breakdown voltage, high on-resistance, and excess gate charges that impact device switching speed.
Thus, there is a need for improved LDMOS device structures and cost-effective manufacturing methods that offer reduced on-resistance, higher breakdown voltage, and lower gate charges.